1. Field of the Invention
The present invention relates to techniques for forming semiconductor device dielectrics. More particularly, the present invention relates to the formation of dielectrics having high dielectric constant values.
2. Description of the Related Art
Designers and semiconductor device manufacturers constantly strive to develop smaller devices from wafers, recognizing that circuits with smaller features generally produce greater speeds. Semiconductor wafer fabrication involves a series of processes used to create semiconductor devices and integrated circuits (ICs) in and on a semiconductor wafer surface. Fabrication typically involves the basic operations of layering and patterning, together with others such as doping, and heat treatments. As the scaling of the Metal Oxide Semiconductor (MOS) transistor proceeds toward deep sub-micron dimensions, the selection of materials used in the layering steps is evolving.
That is, as semiconductor features shrink in size new materials must sometimes be used to ensure that the scaled devices maintain the proper device characteristics after miniaturization. For MOS devices, SiO2 has long been used to isolate the transistor gate from the silicon channel. However, as device dimensions shrink below 100–150 nm, SiO2 becomes unreliable for use as an insulator. At these sizes, the corresponding SiO2 electrical characteristics for the scaled device require a physically thin SiO2 gate dielectric layer. Such a thin SiO2 gate dielectric layer may result in excessive current leakage, i.e., from tunneling. Many other factors determine the leakage current but the primary mechanism involved is direct tunneling in the ultra-thin thickness regime and is a function of the thickness of the dielectric layer.
One class of proposed substitute dielectric materials includes high-k (high-dielectric constant) materials. These materials typically exhibit k's (i.e., relative permitivities or dielectric constants) greater than 5.0 in comparison to the 3.9 k values normally reported for SiO2. The capacitance of a MOS transistor is proportional to the dielectric constant k of the materials and inversely proportional to the distance d between the two electrodes (i.e. in a MOS device, the gate and the channel). Thus, materials with a high dielectric constant k, permit them to exhibit similar electrical characteristics to the SiO2 gate dielectric when deposited in thicker layers.
The use of high-k dielectrics can benefit electronic devices in a variety of ways. Examples of potential high-k applications include the typical dual-gated or triple-gated CMOS transistors on application specific integrated circuits (ASIC) and system-on-chip (SoC) memory devices such as SRAM on system-on-chip electronic components, and designs requiring the shrinkage of large capacitors in analog IC's. That is, the applications of high-k dielectrics may be targeted to CMOS devices to reduce gate leakage, memory devices for increased packing density, and capacitors in analog devices requiring the shrinkage of their physical dimensions.
High-k dielectrics increase the capacitance of a capacitor and facilitate miniaturization. The capacitance of a capacitor is proportional to k and the surface area but inversely proportional to the separation distance between the electrodes. Thus, the capacitance can be maintained even when areas are smaller, if higher k materials are used. Moreover, the higher the k value of the material used to construct the capacitor, the more densely the capacitors can be packed on an integrated circuit chip.
Devices mentioned in each of the categories described above are facing serious difficulties related to the dielectric components of their structures. For example, in CMOS devices, the gate leakage currents in the existing devices are too high. The leakage currents, however, will only be higher in the future generations of devices since the gate dielectrics (SiO2 based) will be even thinner which will result in more charge tunneling. This implies that further shrinkage of the existing CMOS transistors will require thicker dielectric layers while maintaining the same gate capacitance and thus the use of high-k materials for the gate dielectric to avoid rendering the devices unusable.
The needs for high-k materials in memory devices are also significant. Recent SoC products demand a large quantity of memory devices, which inevitably use dielectrics as part of their structures. There is a tendency to reduce the size of these devices so that as many of these devices as possible can be accommodated onto each IC chip. This, however, results in the reduction of the thickness of the dielectrics (usually SiO2 based) so that charge leakage through the dielectrics will become detrimental in the devices of future technology generations.
Further miniaturization of analog IC chips also suggests increased usage of high-k materials. Analog circuits frequently require capacitors with capacitance up to several tens of nF. Capacitors having these electrical characteristics will occupy substantial portions of the IC chips, and hence prevent the shrinking of these IC chips, as well as increase their cost if conventional dielectrics are used.
Current approaches to solving these problems focus on high-k dielectrics. For CMOS devices, replacing the SiO2 based gate dielectrics with high-k dielectrics, it is possible to increase the thickness of the dielectrics without changing the gate capacitance. This will suppress current tunneling, and hence reduce gate leakage currents. A high-k dielectric that can satisfy all the technical requirements for this application, however, has yet to be developed.
In memory devices, it is possible to replace SiO2 with high-k dielectrics so that a thicker dielectric layers to provide the same capacitance and lower leakage currents. However, there is no high-k dielectric that can improve the performance of the memory devices while satisfying the requirements of other devices on the same integrated circuit chip.
Current approaches to the size constraints imposed by capacitors for analog IC chips involve either avoidance of the usage of large capacitors on IC chips or to bond off-chip capacitors onto printed circuit boards. The first approach frequently increases the design effort and cycle time of such chips, while the latter approach unacceptably increases manufacturing costs.
As can be seen from the above, the described problems of these devices can be solved by replacing SiO2 with suitable high-k dielectrics. The major problem, however, is the absence of a high-k dielectric that can be used for all these devices, which frequently co-exist on the same IC chip. That is, no conventional high-k material resolves the varying demands for CMOS gates, memory cells, and capacitors in a satisfactory manner. Accordingly, what is needed is an improved high-k material and process for forming such material that will meet the demands of the various devices.